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Espressif Systems /ESP32-S2-ULP /RTC_CNTL /ULP_CP_TIMER

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Interpret as ULP_CP_TIMER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ULP_CP_PC_INIT0 (ULP_CP_GPIO_WAKEUP_ENA)ULP_CP_GPIO_WAKEUP_ENA 0 (ULP_CP_GPIO_WAKEUP_CLR)ULP_CP_GPIO_WAKEUP_CLR 0 (ULP_CP_SLP_TIMER_EN)ULP_CP_SLP_TIMER_EN

Description

Configure coprocessor timer

Fields

ULP_CP_PC_INIT

ULP coprocessor PC initial address
ULP_CP_GPIO_WAKEUP_ENA

Enable the option of ULP coprocessor woken up by RTC GPIO
ULP_CP_GPIO_WAKEUP_CLR

Disable the option of ULP coprocessor woken up by RTC GPIO
ULP_CP_SLP_TIMER_EN

ULP coprocessor timer enable bit. 0: Disable hardware Timer. 1: Enable hardware timer

Links

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Register License

Copyright 2023 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data